Coreinfo v3.52

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  • 4 minutes to read

Past Mark Russinovich

Published: February 22, 2021

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Introduction

Coreinfo is a command-line utility that shows y'all the mapping betwixt logical processors and the physical processor, NUMA node, and socket on which they reside, besides equally the enshroud's assigned to each logical processor. Information technology uses the Windows' GetLogicalProcessorInformation role to obtain this information and prints it to the screen, representing a mapping to a logical processor with an asterisk eastward.g. '*'. Coreinfo is useful for gaining insight into the processor and enshroud topology of your organization.

Installation

Extract the archive to a directory and and so run Coreinfo past typing from that directory Coreinfo in the panel on a 32 flake Windows version or Coreinfo64 for a 64 scrap version.

Using CoreInfo

For each resource it shows a map of the OS-visible processors that correspond to the specified resources, with '*' representing the applicative processors. For example, on a 4-cadre system, a line in the cache output with a map of shared past cores iii and 4.

Usage: coreinfo [-c][-f][-g][-fifty][-n][-s][-m][-v]

Parameter Description
-c Dump information on cores.
-f Dump cadre feature information.
-g Dump information on groups.
-l Dump information on caches.
-due north Dump information on NUMA nodes.
-s Dump information on sockets.
-one thousand Dump NUMA access toll.
-v Dump only virtualization-related features including support for 2d level address translation.
(requires administrative rights on Intel systems).

All options except -5 are selected by default.

Coreinfo Output: 

              Coreinfo v3.03 - Dump information on system CPU and memory topology Copyright (C) 2008-2011 Marker Russinovich Sysinternals - www.sysinternals.com  Intel(R) Xeon(R) CPU           W3520  @ 2.67GHz Intel64 Family 6 Model 26 Stepping 5, GenuineIntel EM64T           *       Supports 64-bit mode VMX             -       Supports Intel hardware-assisted virtualization SVM             -       Supports AMD hardware-assisted virtualization HYPERVISOR      *       Hypervisor is nowadays HTT             *       Supports hyper-threading  SMX             -       Supports Intel trusted execution SKINIT          -       Supports AMD SKINIT EIST            *       Supports Enhanced Intel Speedstep  NX              *       Supports no-execute page protection PAGE1GB         -       Supports 1GB large pages PAE             *       Supports > 32-fleck concrete addresses PAT             *       Supports Page Attribute Table PSE             *       Supports 4-MB pages PSE36           *       Supports > 32-bit address four-MB pages PGE             *       Supports global bit in page tables SS              *       Supports bus snooping for cache operations VME             *       Supports Virtual-8086 fashion  FPU             *       Implements i387 FP instructions MMX             *       Supports MMX instruction gear up MMXEXT          -       Implements AMD MMX extensions 3DNOW           -       Supports 3DNow! instructions 3DNOWEXT        -       Supports 3DNow! extension instructions SSE             *       Supports Streaming SIMD Extensions SSE2            *       Supports Streaming SIMD Extensions 2 SSE3            *       Supports Streaming SIMD Extensions iii SSSE3           *       Supports Supplemental SIMD Extensions 3 SSE4.ane          *       Supports Streaming SIMD Extensions 4.ane SSE4.2          *       Supports Streaming SIMD Extensions 4.2  AES             -       Supports AES extensions AVX             -       Supports AVX intruction extensions FMA             -       Supports FMA extensions using YMM state MSR             *       Implements RDMSR/WRMSR instructions MTTR            *       Supports Mmeory Type Range Registers XSAVE           -       Supports XSAVE/XRSTOR instructions OSXSAVE         -       Supports XSETBV/XGETBV instructions  CMOV            *       Supports CMOVcc instruction CLFSH           *       Supports CLFLUSH pedagogy CX8             *       Supports compare and exchange 8-byte instructions CX16            *       Supports CMPXCHG16B instruction DCA             -       Supports prefetch from memory-mapped device F16C            -       Supports half-precision instruction FXSR            *       Supports FXSAVE/FXSTOR instructions FFXSR           -       Supports optimized FXSAVE/FSRSTOR educational activity MONITOR         -       Supports MONITOR and MWAIT instructions MOVBE           -       Supports MOVBE instruction PCLULDQ         -       Supports PCLMULDQ pedagogy POPCNT          *       Supports POPCNT instruction SEP             *       Supports fast system call instructions  DE              *       Supports I/O breakpoints including CR4.DE DTES64          -       Can write history of 64-flake co-operative addresses DS              -       Implements memory-resident debug buffer DS-CPL          -       Supports Debug Shop feature with CPL PCID            -       Supports PCIDs and settable CR4.PCIDE PDCM            -       Supports Performance Capabilities MSR RDTSCP          *       Supports RDTSCP education TSC             *       Supports RDTSC teaching TSC-Borderline    -       Local APIC supports one-shot deadline timer xTPR            *       Supports disabling task priority messages  ACPI            *       Implements MSR for ability direction TM              *       Implements thermal monitor circuitry TM2             *       Implements Thermal Monitor two control APIC            *       Implements software-accessible local APIC x2APIC          -       Supports x2APIC  CNXT-ID         -       L1 data cache manner adaptive or BIOS  MCE             *       Supports Machine Bank check, INT18 and CR4.MCE MCA             *       Implements Car Bank check Architecture PBE             *       Supports use of FERR#/PBE# pin  PSN             -       Implements 96-chip processor series number  Logical to Concrete Processor Map: *---  Concrete Processor 0 -*--  Physical Processor one --*-  Physical Processor two ---*  Concrete Processor 3  Logical Processor to Socket Map: ****  Socket 0  Logical Processor to NUMA Node Map: ****  NUMA Node 0  Logical Processor to Cache Map: *---  Data Cache          0, Level ane,   32 KB, Assoc   eight, LineSize  64 *---  Pedagogy Cache   0, Level 1,   32 KB, Assoc   four, LineSize  64 *---  Unified Cache       0, Level ii,  256 KB, Assoc   viii, LineSize  64 -*--  Information Enshroud          1, Level 1,   32 KB, Assoc   8, LineSize  64 -*--  Instruction Cache   1, Level ane,   32 KB, Assoc   4, LineSize  64 -*--  Unified Cache       1, Level ii,  256 KB, Assoc   8, LineSize  64 --*-  Information Cache          2, Level one,   32 KB, Assoc   8, LineSize  64 --*-  Teaching Cache   2, Level 1,   32 KB, Assoc   four, LineSize  64 --*-  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64 ---*  Data Enshroud          3, Level 1,   32 KB, Assoc   8, LineSize  64 ---*  Teaching Cache   3, Level 1,   32 KB, Assoc   four, LineSize  64 ---*  Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64 ****  Unified Cache       iv, Level iii,    8 MB, Assoc  sixteen, LineSize  64  Logical Processor to Group Map: ****  Group 0

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